1. Field of Invention
This invention relates to a semiconductor process, particularly to a method for fabricating a semiconductor device.
2. Description of Related Art
In a conventional process for fabricating strained MOS transistors, a disposable silicon nitride (Dis-SiN) layer is formed covering a NMOS area but exposing a PMOS area to be formed with a stress layer, and is removed after the stress layer is formed. In addition, a thin spacer is usually formed on the sidewall of the NMOS gate before the Dis-SiN layer is formed, which is capable of controlling the overlap width of the later formed NMOS source/drain (S/D) extensions with the NMOS gate. This overlap width will affect the electrical characteristics of the semiconductor device.
However, in the formation of the NMOS S/D extensions after the stress layer is formed, the thin spacer usually has been damaged in the profile or thickness by the prior etching step(s), so the uniformity of the devices is lowered. In addition, in the removal of the Dis-SiN layer, the exposed substrate surface is easily damaged, which may cause some problems in the device reliability and performance.